The present invention relates generally to test circuits for semiconductor devices, and more particularly to circuits that provide internal test result data on the output pins of a semiconductor device.
Semiconductor memory devices typically include one or more memory arrays, each of which includes a large number of memory cells. In a standard mode, in response to an applied address, selected memory cells are accessed and a given operation is allowed to take place (e.g., a read, write, program or erase operation). The memory cells are usually logically arranged into input/output (I/O) groups in such a way that an applied address will access a memory cell from each I/O group. For example, a memory device may include 128 I/O groups, thus, the applied address would access one memory cell from each of 128 I/O groups. Selected of the 128 memory cells can then be output according to the data width of the memory device. That is, if the memory device has a data width of eight bits, an output data path will be provided to only eight of the 128 bits. Such an arrangement can also make use of xe2x80x9cprefetchxe2x80x9d architectures. In a prefetch architecture, all 128 memory cells would be accessed simultaneously, with data paths being provided sequentially according to the data width of the device. For example, in a read operation for a memory device having a 32-bit data width, data from 128 memory cells would be accessed in a single cycle, and then output, 32-bits at a time, on four consecutive clock cycles.
While semiconductor device manufacturing processes continue to improve, at the same time, dimensions continue to shrink and operating speeds continue to increase. Thus, in an attempt to create smaller and faster devices, manufacturing defects can still occur. In order to ensure that defective devices are not supplied to customers, semiconductor devices are usually tested to ensure their functionality. Many such tests involve writing data into and then reading data from, each of the memory cells within the semiconductor memory device. Due to the considerable number of memory cells within a semiconductor memory device, if such tests are undertaken using conventional access operations, a large amount of time is required to test each memory cell in the memory device.
In order to reduce the amount of time required to test a semiconductor memory device, many memory devices include xe2x80x9con-chipxe2x80x9d test circuits. That is, rather than have test equipment generate all of the possible addresses and compare the resulting data with test data, circuits on the memory device itself can test memory cells, and provide data outputs reflecting the results of the test. An example of a prior art on-chip test arrangement for a semiconductor memory device is set forth in FIG. 1.
Referring now to FIG. 1, a prior art semiconductor memory device having an on-chip test circuit is designated by the general reference character 100. The memory device 100 is shown to include a corearray 102 which has a number of memory cells arranged into one or more arrays. The prior art memory device 100 of FIG. 1 is a synchronous dynamic random access memory (DRAM), and so receives conventional input signals, including a system clock signal (CLK), a row address strobe signal (RAS_), a column address strobe signal (CAS_), a write enable signal W_, and address signals (ADD). The input signals are received by a command decoder 104. The command decoder 104 generates internal control signals, including an internal row address strobe signal (INT_RAS), an internal column address strobe signal (INT_CAS), and internal address signals (INT_ADD). In addition, the command decoder 104 generates a test mode signal (TEST_MODE), an output enable signal (OE0), and an internal clock signal (INT_CLK).
According to the applied control signals, the corearray 102 provides access to selected memory cells by way of a number of data I/O lines (I/O0-I/O7). In the arrangement of FIG. 1, particular memory cells are accessed by the INT_ADD signals according to timing established by the INT_RAS and INT_CAS signals. The data I/O lines (I/O0-I/O7) are coupled to a standard data path 106 and a test data path 108. To avoid unduly cluttering the view of FIG. 1, the standard data path 106 illustrates the data path for line I/O0 only. The standard data path 106 is shown to include a data state circuit 110. The data state circuit 110 receives a standard enable signal STD_EN signal and the I/O0 line as inputs, and provides a standard data signal output DATA_STD. When the OE0 signal is high, the data state circuit 110 drives its output DATA_STD according to the I/O0 line signal. When the STD_EN signal is low, the date state driver is placed in a high impedance (hi-Z) state.
The output of the data state circuit 110 is connected to the input of a complementary metal-oxide-semiconductor (CMOS) transfer gate 112. The transfer gate 112, when enabled, provides a data input (DATA) to an output driver circuit 114. The transfer gate 112 is enabled by a READ_CLK signal, and its complement, READ_CLK_.
The output driver circuit 114 also receives a driver output enable signal (OE). When the OE signal is high, the output driver circuit 114 drives a data output (DQ) according to the value of the DATA signal. When the OE signal is low, the output driver circuit 114 is placed in a hi-Z state. The output driver 114 set forth in FIG. 1 is shown to include a CMOS driver stage that includes a p-channel MOS transistor P100 and an n-channel MOS transistor N100. The operation of the two transistors (P100 and N100) is controlled by NAND gate G100, NOR gate G102, and inverter I100. The DATA signal is received as an input to gates G100 and G102, and the OE signal is connected directly to gate G100 as a second input, and by way of inverter I100 as a second input to gate G102. In this arrangement, when the OE signal is low, the output of gate G100 is high and the output of gate G102 is low, resulting in transistors P100 and N100 being turned off. When the OE signal is high, in the event the DATA signal is high, transistor P100 is turned on, and transistor N100 is turned off. In the event the DATA signal is low, transistor P100 is turned off and transistor N100 is turned on.
The STD_EN signal, the READ_CLK and READ_CLK_ signals are provided by a control circuit 116. In a standard mode of operation (such as a read operation), the STD_EN signal is high and the READ_CLK and READ_CLK_ signals will pulse high and low, respectively. Consequently, as data is placed on the I/O0 line, the data state circuit 110 will drive its output according to the logic of line I/O0. Transfer gate 112 will be turned on, resulting in the DATA signal being generated from the logic of line I/O0. The DATA signal will then result in a DQ signal having the same logic as the DATA signal.
The STD_EN, READ_CLK and READ_CLK_ signals are generated by the control circuit 116 in response to the TEST_MODE signal, the OE0 signal, and the INT_CLK signal. The control circuit 116 is shown to include an inverter I102, a three-input AND gate G104, a two-input AND gate G106, and a two input NAND gate G108. The outputs of gates G104 and G106 provide inputs to a two-input OR gate G110. Gate G104 receives the OE0 signal and TEST_MODE signal as inputs, and in addition, receives a pass/fail indication (PASS) from the test data path 108. In a non-test operation (such as a standard read operation), the TEST_MODE signal is low, thus gate G104 provides a low output signal regardless of the state of its other inputs. The TEST_MODE signal is inverted by inverter I102 and applied as one input to gate G106. The other input to gate G106 is the OE0 signal. In this manner, in a non-test mode, gate G106 provides an output that reflects the value of OE0 signal. The output of gate G106 is the STD_EN signal.
The outputs of gates G104 and G106 are further provided as inputs to gate G110. The output of gate G110 is the OE signal. This arrangement results in the OE signal reflecting the OE0 value in a non-test mode.
The OE0 signal is also an input to gate G108. The other input to gate G108 is the INT_CLK signal. The output of gate G108 provides the READ_CLK_ signal, and is further inverted by an inverter I104 to generate the READ_CLK signal. Because the INT_CLK signal is activated (transitions high) in synchronism with the CLK signal, the READ_CLK and READ_CLK_ signals enable the transfer gate 116 in synchronism with the CLK signal (provided the OE0 signal is high).
Having described the operation of the DRAM 100 in a xe2x80x9cstandardxe2x80x9d mode of operation, a parallel test mode of the particular DRAM 100 of FIG. 1 will be described. In the test mode, the standard data path 106 is disabled, preventing the I/O0 line data from reaching the transfer gate 112. In particular, with the TEST_MODE signal high, a low input is provided at gate G106, forcing the output of gate G106 (the STD_EN signal) to be low. The low STD_EN signal results in the data state circuit 110 being placed in the hi-Z state, essentially isolating line I/O0 from the transfer gate 112.
In contrast to the standard data path 106, in the test mode, the test data path 108 provides data to the transfer gate 112. The test data path 108 is shown to include a xe2x80x9ccompressxe2x80x9d circuit 118 that receives all of the I/O lines (I/O0-I/O7) as inputs and provides two compare output signals, CMPB and CMPT, as outputs. The compress circuit 118 xe2x80x9ccompressesxe2x80x9d test data by reducing the output values of lines I/O0-I/O7 into the two signals CMPB and CMPT. This is accomplished by comparing the data of lines I/O0-I/O7 to predetermined values. In particular, in the case of FIG. 1, in the event all of the lines I/O0-I/O7 are low, the CMPT signal will be high and the CMPB signal will be low. Conversely, in the event all of the lines I/O0-I/O7 are high, the CMPT signal will be low, and the CMPB signal will be high. The compress circuit 118 will also indicate if a test fail condition exists (i.e., all the I/O lines are not at the same logic value). In such a case, the CMPT and CMPB signals will both be high.
Within the test data path 108, the CMPT and CMPB signals are received by a test data state circuit 120 and a pass/fail circuit 122. Both the test data state circuit 120 and the pass/fail circuit 122 are enabled by the TEST_MODE signal. When the TEST_MODE signal is low, the test data state circuit 120 and the pass/fail circuit 122 are placed in a hi-Z state. When the TEST_MODE signal is high, the test data state circuit 120 provides a DATA_TST output signal that indicates the logic values of the I/O lines (I/O0-I/O7). In particular, if the I/O lines (I/O0-I/O7) are all high (or the test data indicates a fail condition), the DATA_TST signal will be high. When the I/O lines (I/O0-I/O7) are all low (and no test fail condition exists) the DATA_TST signal will be low.
The pass/fail circuit 122 utilizes the CMPB and CMPT signals to determine if an error condition exists on the I/O lines (I/O0-I/O7). If a pass condition exists, the CMPB or CMPT signals will be at different logic values (indicating that successful test data has been received), and the output of the pass/fail circuit 122 (a PASS signal), will be high. Conversely, when the CMPB and CMPT signals are both high (indicating test failure), the PASS signal will be low.
The DATA_TST and PASS signals are used to provide an output data signal (DQ) that reflects the test results. As shown in FIG. 1, the DATA_TST signal is provided as an input to transfer gate 112. Thus, in a test operation, the output driver 114 drives the DQ output according the logic values of all of the I/O lines (I/O0-I/O7), instead of according to the data of line I/O0. At the same time, the PASS signal is applied to the control circuit 116 and is utilized to enable the output driver 114. Accordingly, when the data test is passed (PASS is high), the output driver 114 will be enabled and the output DQ will be driven high in the event all of the I/O lines (I/O0-I/O7) were high, or low in the event all of the I/O lines (I/O0-I/O7) were low. When the data test indicates an erroneous value has been provided on one or more of the I/O lines (I/O0-I/O7) (PASS is low), the output driver 114 will be placed in a hi-Z state. As shown in FIG. 1, the PASS signal is provided as an input to gate G104 within the control circuit 116. Thus, when the PASS signal is low, the output of gate G104 is forced low. At the same time, a high TEST_MODE signal causes the output of gate G106 to be forced low. With two low inputs, the output of gate G110 (the OE signal) will be low. The low OE signal as applied to the output driver 114 will place the output driver 114 into the hi-Z state.
Referring now to FIG. 2, a timing diagram is set forth illustrating a test operation according to the DRAM 100 of FIG. 1. At time t0, the DRAM 100 is place into the test mode by a predetermined combination of RAS_, CAS_, W_, and ADD values. As a result, the TEST_MODE signal is driven high. The INT_CLK signal follows the CLK signal. The INT_RAS and INT_CAS signals remain low, as the applied RAS_ and CAS_ signals are not timing signals, but rather mode establishing signals. Because an access operation has not taken place at time t0, the OE0 and OE signals are both low. The low OE0 signal causes the READ_CLK signal to remain low. Because no test data has yet been generated, the PASS and DATA signals are both low.
At time t1, now that the DRAM 100 is in the test mode, a test row address (ADD) is applied in conjunction with a low RAS_ signal. The INT_RAS signal is driven high, resulting in selected memory cells being coupled to bit lines within the corearray 102. The data on the bit lines is then amplified.
At time t2, having successfully generated test data on the bit lines, a test column address (ADD) is applied in conjunction with a low CAS_ signal. The INT_CAS signal is driven high, resulting in selected of the bit lines being coupled to the I/O lines (I/O0-I/O7). The resulting I/O line test data are compared with predetermined data values in the compress circuit 118, and the results (the CMPB and CMPT signals) are provided to the test data state circuit 120 and pass/fail circuit 122.
At time t3, the test data state circuit 120 and pass/fail circuit 122 provide the DATA_TST and PASS values as outputs. As noted previously, the DATA_TST signal will be high or low, depending upon the values of the I/O lines (I/O0-I/O7), and the PASS signal will be high or low, depending upon whether or not the data have passed the test.
At time t4, according to the command decoder 104, the OE0 signal transitions high. This results in the OE and READ_CLK signals going high. The transfer gate 112 is enabled, and if the PASS signal is high (the I/O line data have passed the test) the DQ output will be driven according to the DATA_TST value. If the PASS signal is low the output driver 114 will be in the hi-Z state.
At time t5, a particular combination of RAS_, CAS_, W_ and ADD signals are applied to take the DRAM 100 out of the test mode and back into the standard mode.
In the manner described above, the DRAM 100 provide three DQ states to indicate test results, a high logic value for a successful read of all high values, a low logic value for a successful read of all low values, and a hi-Z state in the event the I/O line data fails the test.
A problem related to the parallel testing arrangement of FIG. 1 arises when different data transmission approaches are used. For example, certain types of system bus arrangements require xe2x80x9copen drainxe2x80x9d output drivers (as opposed to CMOS output driver of FIG. 1). In a system that requires open drain output drivers, rather than rely on semiconductor device output drivers that drive an output between a high logic level and a low logic level, an open drain output driver drives an output between a low logic state and a hi-Z state. A high logic state is then established by the bus, which includes a terminating resistor connected between the data output and a terminating voltage. When open drain output driver is in the hi-Z state, the terminating resistor will pull the output to the high logic level.
Because the open output drain driver provides only two states, instead of three, the parallel test circuit of the prior art in not capable of providing a signal that indicates the test data value read (i.e., high or low) as well as the test results (i.e., pass or fail). In light of the use of open drain drivers in semiconductor memory and other devices, it would be desirable to provide some way of providing test data from a semiconductor device having a open drain output driver.
According to the preferred embodiment, a semiconductor memory device includes a parallel data test circuit that generates a pair of test result values. The test result values are provided at an output of the semiconductor memory device. Rather than present the test result data by driving an output between a high voltage, a low voltage, and a high impedance (hi-Z) state, the preferred embodiment drives an output between a high impedance state, a low voltage and an intermediate level, by controlling the amount of current drawn by an open drain output driver.